A conventional digital clock-data recovery (CDR) system consists of circuitry for collecting timing information from an incoming data signal, processing and filtering the timing information to generate clock phasing information, and generating clock signals in accordance with the clock phasing information. Timing information is typically generated by determining whether samples captured in the vicinity of data signal transitions are captured before or after such transitions, thereby yielding a sequence of early/late indications at a peak rate equal to the data rate of the incoming signal. The early/late indications are typically provided to an up/down counter in which the most significant bits constitute a phase count that controls the phase of the recovered clock signals, and the least significant bits constitute a divider-type filter. That is, when the least significant bits overflow or underflow the phase count is incremented or decremented to adjust the phase of the recovered clock signals, thus effecting a divide-by-Q filter in which Q is established by the number of filter bits, R (i.e., Q=2R).
In a plesiochronous system in which clock phases are updated relatively frequently to compensate for a frequency difference between reference clocks provided to the signal transmitter and receiver, a fairly small circuit block may be used to implement the divider-type filter. That is, a filter having a relatively short time-constant is desired, so that a low value of Q and therefore a small number of bits, R, may be used to implement the divider-type filter. By contrast, in a mesochronous system in which the receiver and transmitter receive reference clock signals having exactly the same frequency, but unknown phase, a much lower rate of phase updates is usually desirable, meaning that the value of Q and therefore the number of bits, R, used to implement the divider-type filter go up significantly. For example, at Gigahertz signaling rates, a CDR system may require a divider-type filter large enough to count several thousand early/late indications in order to realize a desired phase update frequency. Unfortunately, such large divider-type filters generally require a substantial amount of combinatorial logic and therefore tend to consume considerable power and die area; a consumption that may be multiplied many times over depending on the number of CDR-based signaling links in the device or system.